Conventional input buffers typically convert an external off-chip signal to an internal on-chip signal. In particular, a TTL (transistor-transistor logic) input buffer used for complementary metal oxide semiconductor (CMOS) devices may perform the function of converting an external signal at a TTL-compatible level into an internal on-chip signal at a CMOS-compatible level. It is also important that this conversion function generate a stable internal signal which has reduced susceptible to noise.
Referring now to FIG. 1, an electrical schematic of an integrated buffer circuit according to the prior art is illustrated. This buffer circuit can perform the above-described function and includes a TTL inversion buffer 11 for inverting and buffering the input signal INPUT (at a TTL level) and a first inversion driver 13 for inverting and buffering the output of the TTL inversion buffer 11. This input buffer also includes a second inversion driver 15 for inverting and buffering the output signal of the first inversion driver 13 and generating an on-chip signal OUTPUT which may be provided to a high internal load. In FIG. 1, reference characters P11 and P12 indicate PMOS transistors and reference characters N11, N12 and N13 indicate NMOS transistors. As will be understood by those skilled in the art, the on-chip signal OUTPUT should be maintained at a stable CMOS-compatible level after each signal transition. To illustrate, an input buffer of a DRAM device may receive a chip enable (CE) signal at a TTL level and convert this chip enable signal to an internal signal for activating the DRAM. In particular, when the chip enable signal is changed from a logic 1 state to logic 0 state, the internal signal OUTPUT changes from a logic 0 state to a logic 1 state to thereby activate the DRAM. Unfortunately, the internal signal OUTPUT generated by the conventional input buffer of FIG. 1 may become distorted due to noise generated by the semiconductor device, as shown by the timing diagram of FIG. 2. Accordingly, the DRAM device may malfunction. Here, as illustrated, the noise may be in the power supply voltage VDD or ground voltage VSS and may be caused by bit line sensing noise or data output noise.
Thus, notwithstanding the above-described TTL-to-CMOS compatible buffer, there continues to be a need for improved buffer circuits which have greater noise immunity.